Calculating display mode values

ABSTRACT

Values are calculated which control the manner in which a display streamer directs the movement of display data. The values are stored in the display streamer.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation application which claimsbenefit of U.S. application Ser. No. 09/579,335, filed May 25, 2000. Thedisclosure of the prior application is considered part of (and isincorporated by reference in) the disclosure of this application.

BACKGROUND

[0002] This invention relates to calculating display mode values.

[0003] A display streamer in a graphics processor requests display datafrom memory to be temporarily stored in a FIFO (first-in first-out) andcontinuously feeds the display data to a display engine. Any break orinterruption in feeding the display data results in visual artifacts inthe final output (display) on a display device, e.g., an analog cathoderay tube (CRT) monitor. Additionally, the memory is usually mostefficient when providing data at a high rate while the graphicsprocessor can usually only use data at a rate that is much lower thanthis high rate.

[0004] To eliminate these visual artifacts and increase efficiency, thedisplay streamer may be programmed with a watermark value and a burstlength value for each display mode supported by the graphics processor.A display mode can be, e.g., a combination including display deviceresolution, color depth or pixel depth, refresh rates, and systemconfiguration. The watermark value represents a FIFO size and fallsbetween the minimum and maximum size of the FIFO, usually expressed inquadwords (QW) that are blocks of eight bytes each.

[0005] When the amount of data in the FIFO drops below the watermarkvalue for the current display mode, the display streamer requests moredisplay data from memory. A display mode's burst length value fallsbetween the minimum and maximum amounts of display data, usuallyexpressed in QW, that the display streamer may request from memory at atime. Analytic models may be used to predict the watermark values andburst length values for each display mode. There are over one hundreddisplay modes.

DESCRIPTION OF DRAWINGS

[0006]FIG. 1 is a block diagram of a computer system in accordance withan embodiment of the invention.

[0007]FIG. 2 is a block diagram of a display system included in thecomputer system of FIG. 1.

[0008]FIG. 3 is a diagram of the display system of FIG. 2.

[0009]FIG. 4 is a flowchart of calculating and programming display modevalues in accordance with an embodiment of the invention.

[0010]FIG. 5 is a graph showing display mode values.

DESCRIPTION

[0011] Referring to FIG. 1, a system 10 includes a central processingunit (CPU) 12 that computes watermark values and burst length values “onthe fly” as the system 10 encounters different display modes. Differentdisplay modes result from different configurations of the system 10. Aconfiguration can be, e.g., a particular combination of multipledisplays, display resolutions, color depths, refresh rates, overlayscaling conditions, video capture conditions, and/or other systemconfigurations. The CPU 12 programs one of the watermark values as acurrent watermark value and one of the burst length values as a currentburst length value into a graphics controller for use in processing thegraphics or video data destined for display on one or more displaydevices 22. The graphics controller could be included in either agraphics/memory controller (GMCH) 14 or a graphics controller (Gfx) 16hanging on an accelerated graphics port (AGP) 18. In this embodiment,assume that the graphics controller is included in the GMCH 14. The GMCH14 uses these values in streaming video or graphics image data. Thisdata can be lines of the image held in main memory, e.g., dynamic randomaccess memory (DRAM) 20, to a display device 22, e.g., a computermonitor, a television, or a floating point display unit.

[0012] Also referring to FIG. 2, a software driver (not shown) and/or ahardware logic unit (not shown) included in the CPU 12 calculates thewatermark values and burst length values using the formulas discussedbelow and programs a display streamer 30 in the GMCH 14 with a watermarkvalue and a burst length value for the current display mode, the presentdisplay mode of the system 10. These values enable the display streamer30 to more efficiently control how and when the data is fetched from anydata source, including local memory 32 and/or main memory 36, e.g., DRAMor synchronous dynamic random access memory (SDRAM), and provided to adisplay mechanism such as a display engine 34, a device that providesthe display device 22 with displayable data. Local memory 32 may beincluded in the GMCH 14, in the Gfx 16, or as a separate unit.

[0013] Any hardware system having a memory that can store data includedin an isochronous data stream, i.e., real-time, non-display datastreams, e.g., modems, LANs (local area networks), and other real-timesystems with event deadlines, can compute watermark and burst lengthvalues “on-the-fly” using the formulas below. The hardware system canuse the software driver and/or the hardware logic unit to compute thewatermark and burst length values and improve the efficiency oftransferring the isochronous data between the memory and a destinationof the isochronous data included in the hardware system.

[0014] Also referring to FIG. 3, a display FIFO 40 located between thememory controller 31 and the display engine 34 eliminates visualartifacts and smooth out delay jitters. Delay jitters manifest asflickers or breaks on the display device 22 and smoothing them outproduces more pleasing video or graphics images, ones with less visualartifacts. The display FIFO 40 holds up to a certain number of quadwords(QW) of data fetched from local memory 32 or main memory 36, ready to beprocessed by the display engine 34 and shown on the display device 22.If the local memory 32 is a separate unit, it can connect to the memorycontroller 31 and use the main memory 36.

[0015] Storing QW of data in the display FIFO 40 can help increaseefficiency of the data transfer between the memory and the graphicscontroller. The memory can provide data at one rate while the graphicscontroller can use data at another, slower rate by storing data thegraphics controller is not ready to use in the FIFO 40.

[0016] The maximum size of the display FIFO 40 depends on the worst casedelay (maximum latency, L_(max)), the FIFO fill rate, and the FIFO drainrate. The arbitration policy in the memory controller 14 determinesL_(max). For example, the display engine 34 may be granted access tolocal memory 32 more frequently than other isochronous clients such as avideo capture engine 42 or an overlay scaling engine 44 and morefrequently than non-isochronous clients such as a two-dimensional engine46. The value of L_(max) represents the maximum amount of time in clockcycles that the display engine 34 may have to wait before winninganother arbitration event and gaining access to local memory 32 toobtain data to occupy the display FIFO 40. The speed of the SDRAM 36determines the FIFO fill rate (φ), expressed in QW per local memoryclock cycle. The FIFO drain rate (δ), expressed in QW per clock cycle,is determined by the rate at which data is consumed by the displayengine 34. The display resolution and the refresh rate contribute to δas shown below.

[0017] The display streamer 30 uses the watermark value (λ) and theburst length value (β) calculated by the driver and/or the hardwarelogic unit in the CPU 12 and programmed into a register included in thedisplay streamer 30 in continuously monitoring the level of data in thedisplay FIFO 40 and ensuring that the display engine 34 receives acontinuous flow of data. If the FIFO level falls below λ, the displaystreamer 30 issues a request in a burst action to local memory 32 ormain memory 20, 36 for an amount of data equal to β to occupy thedisplay FIFO 40.

[0018] The driver and/or hardware logic unit in the CPU 12 chooses λ asa value between a minimum watermark value (λ_(min)) and a maximumwatermark value (λ_(max)). λ_(min) is the value which avoids FIFOunderflows and delay jitter. λ_(min) is given by:

λ_(min) =L _(max)×δ

[0019] Because this formula likely returns λ_(min) as a floating pointnumber and because computer systems operate with integers, the driverand/or hardware logic unit computes λ_(min) with a ceiling subroutine asthe smallest integer value greater than the floating point value ofλ_(min). A λ_(min) at this integer value helps the display FIFO 40 avoidunderflows because λ_(min) is greater than the FIFO drain during L_(max)cycles of waiting.

[0020] The amount of data in QW (β) that the display streamer 30requests in response to detecting a data level below λ in the displayFIFO 40 falls between a minimum burst length value (β_(min)) and amaximum burst length value (β_(max)) β_(min) is given by:$\beta_{\min} = {\lambda_{\min} \times \left( \frac{\phi}{\phi - \delta} \right)}$

[0021] As with λ_(min), the driver and/or hardware logic unit computesβ_(min) with a ceiling subroutine as the smallest integer value greaterthan the floating point value of β_(min). This integer β_(min) valueensures that the display streamer 30 requests enough QW to guaranteethat the level of the display FIFO 40 meets or exceeds λ_(min) at theend of the burst.

[0022] To ensure that the display FIFO 40 does not overflow, the displaystreamer 30 should not request more QW than a maximum burst length value(β_(max)) in a given burst. β_(max) is given by:${\beta_{\max} = {\left( {\Phi - \lambda_{\min}} \right) \times \left( \frac{\phi}{\phi - \delta} \right)}},$

[0023] where Φ equals the size of the display FIFO 40 in QW. Since thisβ_(max) formula likely returns a floating point value, the driver and/orhardware logic unit uses a floor subroutine to calculate an integerβ_(max) value that is the largest integer value less than the floatingpoint value of β_(max).

[0024] Also to help prevent overflow, the maximum watermark level(λ_(max)) indicates the maximum amount of data that the display FIFO 40may contain when the display streamer 30 begins a burst withoutoverflowing the display FIFO 40 with the requested data. λ_(max) isgiven by:

λ_(max)=Φ−(L _(max)×δ)

[0025] As with β_(max), the driver and/or hardware logic unit uses afloor subroutine to calculate an integer value of λ_(max) that is thelargest integer value less than the floating point value of λ_(max).

[0026] Also referring to FIG. 4, the driver and/or hardware logic unitin the CPU 12 uses a process 50 to calculate the watermark value and theburst length value for a current display mode. The process 50 begins(52) by determining (54) any constraints of the system hardware underthe current display mode from the graphics/memory controller 14,graphics controller 12, and/or the display device 22. Such constraintsmay include memory speed, multiple displays, overlay scaling functions,and/or video capture functions. For example, in one current displaymode, the display FIFO 40 size is 48 QW, local memory 32 is running at133 MHz and the worst case latency (L_(max)) for the display streamer 30is forty cycles. The driver and/or hardware logic unit also identifies(56) parameters of the display device 22 such as supportableresolutions, color depth, and refresh rates. In the current displaymode, the display device 22 has a 1280×1024 resolution running at a 100Hz refresh rate in 16 bpp (bits per pixel) mode. Based on theseconstraints and parameters, the driver and/or hardware logic unit cancalculate (58) φ, the FIFO fill rate. Assume that φ equals one in thecurrent display mode. The driver and/or hardware logic unit maydetermine (54) the hardware constraints and identify (56) the displaydevice's parameters in any order.

[0027] The driver and/or hardware logic unit then determines (60) if Φ,the size of the display FIFO 40, is large enough for a specified drainrate δ and L_(max) using the comparative formula:

Φ>2×L _(max)×δ,

[0028] where δ equals approximately 0.357 and is given by:$\delta = {\left( {{display}\quad {clock}\quad {frequency}} \right) \times \left( \frac{{bytes}\quad {per}\quad {pixel}}{{bytes}\quad {per}\quad {QW} \times {memory}\quad {speed}} \right)}$

[0029] The display clock frequency (DCF) depends on the current displaymode and can be expressed in an empirical formula as:

DCF=(horizontal resolution)×(vertical resolution)×(refresh rate)×1.45,

[0030] where 1.45 is a multiplying factor. Other methods may be used tocalculate the DCF, e.g., a table-based method or a Video ElectronicsStandards Association generalized timing formula (VESA GTF). If Φ is notlarge enough, then the display FIFO 40 is too small to handle therequirements of the current display mode and the process 50 fails (62).If Φ is large enough, then the driver and/or hardware logic unit mayproceed to calculate (64) the watermark value and the burst length valuefor the current display mode.

[0031] The driver and/or hardware logic unit calculates

[0032] integer values for λ_(min), λ_(max), β_(min), and β_(max) asdescribed above. In the current display mode, they respectively equalfifteen, thirty-three, twenty-four, and fifty-one. The driver and/orhardware logic unit compares (66) β_(min) and β_(max) to see if thesystem 10 can accommodate the current display mode. If β_(max) is lessthan β_(min), then the process fails (62), and the current display modeis unsupportable. Otherwise, the driver and/or hardware logic unitcompares (68) λ_(min) and λ_(max). The driver and/or hardware logic unitmay compare (66, 68) either burst length values or watermark valuesfirst. If λ_(max) is greater than λ_(min), then the process 50 fails(62). Otherwise, the driver and/or hardware logic unit chooses (70) awatermark value λ between λ_(min) and λ_(max) and a burst length value βbetween β_(min) and β_(max).

[0033] Also referring to FIG. 5, the driver and/or hardware logic unitchooses (70) λ and β for the current display mode from within a region80 defined by λ_(min), λ_(max), β_(min), and β_(max). All of the pointswithin the region 80 are permissible (supportable by the system 10) λand β pairs. The driver and/or hardware logic unit preferably chooses(70) λ and β from a point in the lower left corner of the region 80.Specifically, λ is chosen (70) as the integer value of λ_(min) and β ischosen (70) as:${\beta = {{{ceil}\left( \frac{\beta_{\min}}{8} \right)} \times 8}},$

[0034] where “ceil” indicates the ceiling subroutine explained above.This equation forces β to meet or exceed β_(min) and be a multiple ofeight so that the display streamer 30 can request an integer number ofQW. In other embodiments, the “eights” in the above equation may equalany number, including one. Note that the region 80 shrinks for higherresolutions and refresh rates. The region 80 may not contain anypermissible points indicating an unsupportable display mode. The driverand/or hardware logic unit programs (72) the chosen λ and β values intothe display streamer 30 and the process 50 ends (74).

[0035] Other embodiments are within the scope of the following claims.

What is claimed is:
 1. A method of determining buffer managementinformation for a data processing system comprising: determining alatency parameter based on a first system configuration of the dataprocessing system, the latency parameter representing a latency timeamount between a display data request and delivery of display data to adisplay buffer; determining a buffer drain rate based on a first displaymode of the data processing system; and calculating one or more buffermanagement parameters based on at least the latency parameter and thebuffer drain rate.
 2. The method of claim 1, further comprising:determining a buffer fill rate based on a buffer configuration; andcalculating at least one of the one or more buffer management parametersbased on the buffer fill rate.
 3. The method of claim 1, furthercomprising: calculating at least one of the one or more buffermanagement parameters based on a buffer size.
 4. The method of claim 1,wherein the one or more buffer management parameters comprise awatermark level.
 5. The method of claim 4, wherein the watermark levelcomprises a lower bound of a desired watermark level range.
 6. Themethod of claim 4, wherein the watermark level comprises an upper boundof a desired watermark level range.
 7. The method of claim 1, whereinthe one or more buffer management parameters comprise a burst length. 8.The method of claim 7, wherein the burst length comprises a lower boundof a desired burst length range.
 9. The method of claim 7, wherein theburst length comprises an upper bound of a desired burst length range.10. The method of claim 1, further comprising: detecting a change fromthe first display mode to a second display mode; and calculating atleast one of the one or more buffer management parameters based on thesecond display mode.
 11. The method of claim 1, further comprising:detecting a change from the first system configuration to a secondsystem configuration; and calculating at least one of the one or morebuffer management parameters based on the second system configuration.12. The method of claim 1, wherein the latency parameter represents amaximum expected latency time amount for the first system configurationof the data processing system.
 13. The method of claim 1, wherein thefirst display mode is characterized by at least one of a first refreshrate, a first display resolution, and a first color depth.
 14. Themethod of claim 1, wherein the first system configuration ischaracterized at least by a buffer memory type.
 15. An apparatuscomprising: a display part which directs movement of display data, thedisplay part including a buffer to store display data to be displayed ona display screen; and a data computing system configured to calculateone or more buffer management parameters based on a latency parameterbased on a first system configuration and a buffer drain rate based on afirst display mode; wherein the latency parameter represents a latencytime amount between a display data request and delivery of display datato the buffer; and wherein the buffer drain rate represents a rate atwhich the display data is read from the buffer.
 16. The apparatus ofclaim 15, wherein the data computing system is further configured tocalculate at least one of the one or more buffer management parametersbased on a buffer fill rate, the buffer fill rate based on aconfiguration of the buffer.
 17. The apparatus of claim 15, wherein thedata computing system is further configured to calculate at least one ofthe one or more buffer management parameters based on a buffer size. 18.The apparatus of claim 15, wherein the one or more buffer managementparameters comprise a watermark level.
 19. The apparatus of claim 18,wherein the watermark level comprises a lower bound of a desiredwatermark level range.
 20. The apparatus of claim 18, wherein thewatermark level comprises an upper bound of a desired watermark levelrange.
 21. The apparatus of claim 15, wherein the one or more buffermanagement parameters comprise a burst length.
 22. The apparatus ofclaim 21, wherein the burst length comprises a lower bound of a desiredburst length range.
 23. The apparatus of claim 21, wherein the burstlength comprises an upper bound of a desired burst length range.
 24. Theapparatus of claim 15, wherein the data computing system is furtherconfigured to detect a change from a first display mode to a seconddisplay mode, and in response to the detecting is further configured tocalculate at least one of the one or more buffer management parametersbased on the second display mode.
 25. The apparatus of claim 15, whereinthe data computing system is further configured to detect a change froma first system configuration to a second system configuration, and inresponse to the detecting is further configured to calculate at leastone of the one or more buffer management parameters based on the secondsystem configuration.
 26. The apparatus of claim 15, wherein the latencyparameter represents a maximum expected latency time amount for thefirst system configuration.
 27. The apparatus of claim 15, wherein thefirst display mode is characterized by at least one of a first refreshrate, a first display resolution, and a first color depth.
 28. Theapparatus of claim 15, wherein the first system configuration ischaracterized at least by a first buffer memory type.
 29. An articlecomprising a storage medium which stores computer-executableinstructions, the instructions causing a computer to perform operationscomprising: determining a latency parameter based on a first systemconfiguration of the data processing system, the latency parameterrepresenting a latency time amount between a display data request anddelivery of display data to a display buffer; determining a buffer drainrate based on a first display mode; and calculating one or more buffermanagement parameters based on at least the latency parameter and thebuffer drain rate.
 30. The article of claim 29, the operations furthercomprising: determining a buffer fill rate based on a bufferconfiguration; and calculating at least one of the one or more buffermanagement parameters based on the buffer fill rate.
 31. The article ofclaim 29, the operations further comprising: calculating at least one ofthe one or more buffer management parameters based on a buffer size. 32.The article of claim 29, wherein the one or more buffer managementparameters comprise a watermark level.
 33. The article of claim 32,wherein the watermark level comprises a lower bound of a desiredwatermark level range.
 34. The article of claim 32, wherein thewatermark level comprises an upper bound of a desired watermark levelrange.
 35. The article of claim 29, wherein the one or more buffermanagement parameters comprise a burst length.
 36. The article of claim35, wherein the burst length comprises a lower bound of a desired burstlength range.
 37. The article of claim 35, wherein the burst lengthcomprises an upper bound of a desired burst length range.
 38. Thearticle of claim 29, the operations further comprising: detecting achange from the first display mode to a second display mode; andcalculating at least one of the one or more buffer management parametersbased on the second display mode.
 39. The article of claim 29, theoperations further comprising: detecting a change from the first systemconfiguration to a second system configuration; and calculating at leastone of the one or more buffer management parameters based on the secondsystem configuration.
 40. The article of claim 29, wherein the latencyparameter represents a maximum expected latency time amount for thefirst system configuration of the data processing system.
 41. Thearticle of claim 29, wherein the first display mode is characterized byat least one of a first refresh rate, a first display resolution, and afirst color depth.
 42. The article of claim 29, wherein the first systemconfiguration is characterized at least by a buffer memory type.
 43. Asystem, comprising: a display; a display part which directs movement ofdisplay data to the display, the display part including a buffer tostore display data to be displayed on the display; and a data processorconfigured to calculate one or more buffer management parameters basedon a latency parameter based on a first system configuration and abuffer drain rate based on a first display mode; wherein the latencyparameter represents a latency time amount between a display datarequest and delivery of display data to the buffer; and wherein thebuffer drain rate represents a rate at which the display data is readfrom the buffer.
 44. The system of claim 43, wherein the data processoris further configured to calculate at least one of the one or morebuffer management parameters based on a buffer fill rate, the bufferfill rate based on a configuration of the buffer.
 45. The system ofclaim 43, wherein the data processor is further configured to calculateat least one of the one or more buffer management parameters based on abuffer size.
 46. The system of claim 43, wherein the one or more buffermanagement parameters comprise a watermark level.
 47. The system ofclaim 46, wherein the watermark level comprises a lower bound of adesired watermark level range.
 48. The system of claim 46, wherein thewatermark level comprises an upper bound of a desired watermark levelrange.
 49. The system of claim 43, wherein the one or more buffermanagement parameters comprise a burst length.
 50. The system of claim49, wherein the burst length comprises a lower bound of a desired burstlength range.
 51. The apparatus of claim 49, wherein the burst lengthcomprises an upper bound of a desired burst length range.
 52. The systemof claim 43, wherein the data processor is further configured to detecta change from a first display mode to a second display mode, and inresponse to the detecting is further configured to calculate at leastone of the one or more buffer management parameters based on the seconddisplay mode.
 53. The system of claim 43, wherein the data processor isfurther configured to detect a change from a first system configurationto a second system configuration, and in response to the detecting isfurther configured to calculate at least one of the one or more buffermanagement parameters based on the second system configuration.
 54. Thesystem of claim 43, wherein the latency parameter represents a maximumexpected latency time amount for the first system configuration.
 55. Thesystem of claim 43, wherein the first display mode is characterized byat least one of a first refresh rate, a first display resolution, and afirst color depth.
 56. The apparatus of claim 43, wherein the firstsystem configuration is characterized at least by a first buffer memorytype.